In recent years, recording densities of information storage devices, such as hard disk devices and optical disk devices, have been increased. However, when a signal is recorded at a high density on an information storage device, an amplitude difference may occur in a reproduced signal (analog signal) according to variations in cycles of the recorded signal when the recorded signal is reproduced. This problem is caused because the amplitude of a high-frequency component of the reproduced signal is reduced as the recording density is increased. As a main factor responsible for the reduction in the amplitude, there is an inter symbol interference (ISI). Therefore, the information storage device requires, with an increase in the recording density, signal processing that compensates for a reduction in the amplitude of the high-frequency component of the reproduced signal.
Conventionally, when a reproduced signal (analog signal) is subjected to analog signal processing in an information storage device, a reduction in signal amplitude of a high-frequency component is compensated for by using an analog equalizer. An analog equalizer has an equalization characteristic for passing a signal component of a desired frequency and, simultaneously, providing a gain. Therefore, by adjusting the equalization characteristic to a desired frequency, a reduction in the signal amplitude can be selectively compensated.
There are two methods described below as conventional methods for compensating for a reduction in signal amplitude of a high-frequency component when a reproduced signal (analog signal) is subjected to a digital signal processing.
A first method includes waveform-equalizing an analog signal using an analog equalizer, and thereafter, converting the analog signal into a digital signal. Hereinafter, a conventional equalization apparatus for realizing this first method will be described with reference to FIG. 13. Generally, an information storage device is provided with an equalization apparatus. In the equalization apparatus shown in FIG. 13, initially, an analog filter 67 receives an analog signal, and removes signal components that are unnecessary for waveform equalization. Next, an analog equalizer 87 waveform-equalizes the analog signal outputted from the analog filter 67. At this time, the analog equalizer 87 is given an equalization characteristic that allows high-frequency components of the analog signal to pass. Thereby, a reduction in signal amplitude can be selectively compensated. Next, an A/D converter 57 converts the analog signal 117 outputted from the analog equalizer 87 into a digital signal. Then, a binarizer 37 binarizes the digital signal 157 outputted from the A/D converter 57.
A second method employs a digital equalizer. In this case, a digital equalizer for waveform-equalizing a digital signal is provided in a stage subsequent to an A/D converter. After an analog signal is converted into a digital signal, the digital signal is waveform-equalized by the digital equalizer. When the digital equalizer is employed, however, the resolution of the A/D converter must be enhanced. The reason is as follows. When the resolution of the A/D converter is high, required information can be satisfactorily obtained from the high-frequency component in which the signal amplitude is reduced, when performing A/D conversion of the analog signal before waveform equalization and having a large difference in amplitude. In order to enhance the resolution of the A/D converter, there is a method of increasing the number of bits to be A/D converted.
Hereinafter, a description will be given of problems that occur when a reproduced signal in which an amplitude difference has occurred is waveform-equalized using an analog equalizer or a digital equalizer as mentioned above.
When an analog equalizer is employed, a problem occurs when the frequency of the analog signal to be waveform-equalized changes with the passage of time like the reproduced signal obtained by CAV reproduction. In this case, it is necessary to change the equalization characteristic of the analog equalizer in accordance with the frequency of the analog signal, resulting in an increase in the circuit scale and a reduction in the signal processing speed.
Furthermore, when the analog equalizer is employed, a problem occurs when a signal processing device, such as the conventional equalization apparatus shown in FIG. 13, is realized by a system LSI. When realizing a signal processing device by a system LSI, it is necessary to integrate, on a single chip, an analog circuit, a digital circuit, a memory, and the like which have conventionally been constituted as different LSI circuits. Amongst these circuits, the analog circuit occupies a very large area in the system LSI (CMOS). That is, the analog circuit causes an increase in cost.
On the other hand, when a digital equalizer is employed, it is necessary to increase the A/D resolution of the previous-stage A/D converter. Because the circuit scale of the A/D converter increases in proportion to the number of bits to be A/D converted, the circuit scale of the A/D converter increases when the A/D resolution is increased. Further, circuit delay is increased when the resolution is increased, resulting in a reduction in the signal processing speed.